1. Field of the Invention
This invention relates to a memory system using semiconductor memory to be used for the purpose of protecting copyrights. The invention also relates to a control method of electrically erasable and programmable nonvolatile semiconductor memory, especially useful for use to NAND EEPROM (electrically erasable and programmable read-only memory).
2. Description of the Prior Art
A flash memory card FMC as shown in FIG. 1 has become of major interest lately as a recording medium of portable information devices such as digital still cameras, PDA (personal digital assistant), for example. The flash memory card FMC is a thin plastic package having formed a slight recess holding a built-in flash memory device FM with 22-pin planar electrodes. The flash memory card FMC can exchange data with a host system (personal computer) when electrically connected to the host system via a connector. For example, using a PC card adapter, any file on the flash memory card can be readily delivered to the personal computer.
However, since a memory system using the flash memory FM can easily copy any files including copyrighted ones, such as musical data, and infringement of copyrights has been an issue of this system.
Apart from this, electrically rewritable EEPROM is known as a sort of flash memory. Especially, NAND EEPROM using a NAND cell made by serially connecting a plurality of memory cells has attracted attention as being available for high integration. A memory transistor of NAND EEPROM, has a FETMOS structure in which a floating gate (charge storage layer) and a control gate are stacked on a semiconductor substrate via an insulating film. Then, a plurality of memory transistors are serially connected, with a source and a drain commonly used by every two adjacent memory transistors, to form a single-unit NAND cell, and the NAND cell is connected to a bit line. A number of such NAND cells in a matrix arrangement form a memory array.
A memory array of NAND EEPROM is made up of a plurality blocks. If a single NAND cell has 16 stages, then each block includes 16 word lines for selecting the NAND cells and memory cells within a range where these word lines are continuous. This one block is the minimum unit of collective erasure in flash memory configured to erase data collectively. Each range with memory transistors under one word line is normally called one page.
EEPROM flash memory is now being remarked as not only being rewritable like DRAM but also maintaining storage of data by its nonvolatility even after power supply is cut. In applications of EEPROM flash memory, there is the demand for limiting free rewriting in a part of its memory region and for designing it as OTP (one time PROM) permitting data writing only once.
The demand arises, for example, in devices having a flash memory system for intake and transfer of musical data, for example, which are subjects of the serious copyright problem, when duplication of musical data must be limited to a certain extent. More specifically, in a memory system using EEPROM flash memory, it is requested to store a mark data in an OTP region as an irreversible change of state of a chip every time when the EEPROM flash memory is accessed, accompanied by the task of rewriting data thereon, and to permit the irreversible change of state only predetermined times.